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Lead design verification for complex SoC and IP designs, owning verification planning, SystemVerilog/UVM environments, coverage closure, and RTL-to-gate-level simulation. Work with RTL, analog, architecture, and silicon validation teams; mentor a team of verification engineers. Tools include Xcelium and VCS, with protocol work on I2C/I3C, SPI, JTAG, AMBA, and OBI.
Design Verification Lead
Reports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.
About the Role
We are seeking an experienced and hands-on Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated regression flows. This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.
Key Responsibilities
Qualifications
This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
Preferred Qualifications
Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $160k - $190k
