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The job board for developers. Find your next role at companies that value great engineering.

ยฉ 2023-2026 . All rights reserved.

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Hardware Engineer, Design Verification

Normal Computing Corporation ยท New York; London; Mountain View

Extracted from the posting

Base
$200,000 โ€“ $400,000
Remote
Hybrid, 3 days/week in office; Mountain View, NY, London
Stack
SystemVerilog, UVM, SystemVerilog Assertions, Cadence Xcelium

Design verification engineer for Normal's internal physics-inspired ASICs, owning end-to-end verification from planning through tapeout, including testbenches, assertions, coverage closure, and regression infrastructure. Also building AI-assisted verification workflows for spec analysis, testbench generation, and debugging. Stack is SystemVerilog, UVM, SVA, Python, and Tcl, with Cadence or Synopsys EDA tools.

Normal Computing | Build with Us

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

The Role

Hybrid: 3 days a week in the office, in Mountain View, New York or London.

As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs from architecture through tapeout, and help set the bar for the AI-assisted verification flows we are building for ourselves. You will own verification of complex IPs and subsystems, develop reusable verification infrastructure, and establish methodologies that enable efficient, scalable verification across our silicon programs.

You will also work closely with our architecture, RTL, and software teams to integrate AI-assisted tools into everyday verification workflows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.

What You Will Own

  • ASIC Design Verification: Own end-to-end verification of Normal's internal ASICs, including verification planning, testbench development, assertions, functional coverage, regression, and coverage closure through tapeout.
  • Verification Architecture & Methodology: Develop scalable SystemVerilog/UVM verification environments, reusable VIP, scoreboards, reference models, and verification methodologies across IP, subsystem, and SoC levels.
  • AI-Native Verification Workflows: Develop and integrate AI-assisted verification workflows, including specification analysis, test planning, testbench generation, debugging, and coverage closure. Review AI-generated verification collateral and help define what good looks like, so the tools the team builds raise the bar rather than lower it.
  • Verification Infrastructure & Tooling: Build and maintain regression infrastructure, CI/CD integration, coverage analysis, and EDA tool flows to support efficient and repeatable ASIC verification.
  • Cross-Functional Collaboration: Work closely with architecture, RTL design, physical design, and software teams to identify verification requirements, resolve design ambiguities, and drive silicon quality.

What Makes You a Great Fit

  • 5+ years of experience in digital design verification for complex ASICs, SoCs, or IPs
  • Advanced proficiency in SystemVerilog, UVM, SystemVerilog Assertions (SVA), and constrained-random verification
  • Proven experience in end-to-end verification, including verification planning, testbench architecture, stimulus generation, scoreboards, and functional coverage closure
  • Strong understanding of industry-standard protocols such as AXI, APB, AHB, or other SoC interconnects
  • Experience with EDA simulation, debugging, and coverage tools such as Cadence Xcelium, SimVision, vManager, Synopsys VCS, or Verdi
  • Strong scripting and automation skills using Python, Tcl, or similar languages
  • Experience developing reusable verification environments and debugging complex RTL and system-level issues
  • Strong communication and collaboration skills, with the ability to work across hardware and software teams

Bonus Points

  • Experience building verification infrastructure and methodologies from the ground up for a new ASIC program
  • Hands-on experience using LLMs, AI coding assistants, or agentic tools for RTL design and verification
  • Experience with formal verification, power-aware verification, or emulation
  • Exposure to AI accelerators, memory subsystems, in-memory computing, or unconventional compute architectures

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.

Compensation: $200K - $400K

Technologies

SystemVerilogUVMSystemVerilog AssertionsCadence XceliumSynopsys VCSVerdivManagerPythonTclAXI
Normal Computing Corporation
Normal Computing Corporation
Website

Job details

TypeFull-time
Work ModeHybrid
LevelSenior
Location๐Ÿ‡บ๐Ÿ‡ธMountain View, CA๐Ÿ‡บ๐Ÿ‡ธNew York, NY
Salary$200,000 - $400,000
PostedNov 05, 2026
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