At SF Tensor, we're building the future of high-performance compute

We firmly believe that the future of AI depends on the unglamorous: rethinking and rebuilding the stack, all the way down. From the hardware underneath it to the compiler targeting it and the cloud running it. Right now those three things fight each other and that friction shows up as a tax on every researcher trying to build something ambitious. We're here to axe that tax and make compute faster, cheaper and more available. When we succeed, compute will be portable enough that "which cloud, which chip" stop being something you worry about.

To achieve this, we are building our Kernel Optimizer, which takes code and finds its fastest possible form for whatever vendor and cluster topology you point it at, automatically, as well as the Model Foundry which manages the runs, makes research easier and moves workloads across clouds and chips as prices and availability ship, instead of leaving you locked into whatever vendor you signed with first.

We're backed by Susa Ventures, Y Combinator, along with some great funds and angels including Max Mullen and Paul Graham, as well as founders and executives at Neuralink, Notion and AMD. We're looking for researchers, engineers and organizations who agree with the basic premise: you don't get the next leap in AI without a leap in compute first.

About the Role

We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform, constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space, with agents, with RL, with anything that works and still guarantee the result. It's why we hold #1 on NVIDIA's own kernel benchmark across hundreds of production kernels.

For our search to work, we need to run an enormous amount of untrusted, freshly generated kernels on real silicon, quickly and safely, which is why we're hiring a Member of Technical Staff for Sandbox Infrastructure to build the layer that makes it possible: a serverless GPU container service across NVIDIA, AMD, TPU and Trainium, at a scale and fidelity nobody sells off the shelf. It needs to run three things: (1) our compiler measures every candidate program inside it, so a noisy or unfair sandbox directly corrupts the reward signal the search learns from, (2) our own post-training runs inside it (e.g., when we RL a model on AMD kernel engineering, every rollout is in a sandbox) and (3) customer workloads that require isolation, such as their RL rollouts, run on it too.

We already do this on NVIDIA and AMD, including having rolled AMD GPU support in gVisor . The work now is depth and breadth, adding support for more vendors, higher fidelity instrumentation, faster cold starts and more features. A lot of our sandboxes need to run on spot pools without losing works, they can span multiple GPUs and sometimes multiple nodes, they need to survive failure and preemption as well as live-migration (which our stack does while keeping sockets intact so that instances can relocate mid-flight while still streaming data in or out without a hiccup).