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The job board for developers. Find your next role at companies that value great engineering.

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17 matches
NewestHighest base
OLIX

Senior Analog Layout Designer

today
OLIX · Austin, TX
$292k–292kOn-siteFull-timeCadence Virtuoso · Calibre
Taara

Principal Analog/Mixed-Signal ASIC Design Engineer

today
Taara · Sunnyvale, CA
$258k–294kHybridFull-timeCalibre · Git
Taara

Product Manager- Software Products

today
Taara · Sunnyvale, CA
$160k–180kHybridFull-timePython · Calibre
Taara

UX Designer

today
Taara · Sunnyvale, CA
$140k–160kHybridFull-timePython · Calibre
Taara

Senior High-Speed Photonic Design Engineer

today
Taara · Sunnyvale, CA
$220k–270kHybridFull-timeHFSS · ADS
Taara

Lead Analog/Mixed-Signal ASIC Design Engineer

today
Taara · Sunnyvale, CA
$258k–294kHybridFull-timeCalibre · Git
Taara

Director of Optical and Mechanical

today
Taara · Sunnyvale, CA
$210k–260kHybridFull-timePython · Calibre
Taara

Director of Product Management - Hardware

today
Taara · Sunnyvale, CA
$200k–250kOn-siteFull-timePython · Calibre
Taara

Senior Photonic Circuits Design Engineer

today
Taara · Sunnyvale, CA
$220k–270kHybridFull-timeLumerical · VPIphotonics
Taara

Board Design Engineer

today
Taara · Sunnyvale, CA
$160k–210kHybridFull-timeCadence Virtuoso · Calibre
Normal Computing Corporation

Physical Design Lead

today
Normal Computing Corporation · Mountain View, CA
$200k–400kHybridFull-timeInnovus · IC Compiler II
Normal Computing Corporation

Hardware Engineer, Physical Design

today
Normal Computing Corporation · Mountain View, CA
$200k–400kHybridFull-timeInnovus · IC Compiler II
Lumilens

MMIC Design Engineer

today
Lumilens · San Jose, CA
On-siteFull-timeCadence EMX · Cadence Virtuoso
Lumilens

EDA & CAD Engineer

today
Lumilens · San Jose, CA
On-siteFull-timeCadence Virtuoso · Spectre
Lumilens

Analog Layout Lead

today
Lumilens · San Jose, CA
On-siteFull-timeCadence Virtuoso · Spectre
Lumilens

DSP Engineer

today
Lumilens · San Jose, CA
On-siteFull-timePython · Perl
Lumilens

Sr. Physical Design Engineer

today
Lumilens · San Jose, CA
On-siteFull-timeSynopsys ICC2 · Cadence Innovus
OLIX

Senior Analog Layout Designer

OLIX · 🇺🇸 Austin, TX · posted today
ApplyFull posting

Extracted from the posting

Base
$292,000 – $292,000
Equity
Meaningful stock options
Remote
On-site
Visa
Eligibility depends on citizenship/residency; restricted countries listed
Stack
Cadence Virtuoso, Calibre, Pegasus, SKILL

TL;DR

Creates analog layouts for RX/TX lane macros and supports lane-level integration. Requires 7+ years of analog layout, TSMC FinFET experience at 2nm to 5nm, and expertise in Cadence Virtuoso and Calibre/Pegasus. Work covers ADC, DAC, TIA, CDR, PLL, and LDO macros.

About OLIX →

The full posting


About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.


Role

As a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.


Skills and Experience

  • 7+ years of Analog Layout Design experience
  • Understanding of the Semiconductor Fabrication process and device/layout cross-sections
  • Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm
  • Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)
  • Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation
  • Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation
  • Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications
  • Expert-level knowledge of EM/IR analysis
  • Expert-level knowledge of Cadence Virtuoso and Calibre/Pegasus verification tools
  • Understanding of ESDs and Clamps, and their layout considerations
  • Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE
  • Experience with lane integration and tape out versifications
  • Experience working with revision-controlled design libraries
  • Good communication skills
  • Knowledge of SKILL, TCL, and Python scripting is a plus


Compensation & Equity

  • Competitive Salary: Commensurate with your experience, skills, and location
  • Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it
  • Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
  • Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security
  • Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

    Compensation: $292K