Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking a skilled and driven Silicon Platform Engineer to join the System-on-Chip platform team that works on IP integration, chip-level verification, and firmware development. This is a System-on-Chip design, integration and verification role, working at the intersection of hardware and software. You will shape the platform from IP bring-up through full-chip validation: defining testbenches, authoring test firmware, and implementing critical chip features in silicon. This is a hands-on role with broad impact across the hardware development cycle.

Core Responsibilities

• IP Integration and Verification - IP Integration: Evaluate, integrate, and verify IP blocks within the chip, ensuring correct connectivity, configuration, and interoperability across the platform. - Feature and Module Firmware: Author targeted test firmware to bring up and verify individual IP blocks and hardware features at the module level. - Subsystem Firmware: Develop subsystem-level test firmware to validate interactions between integrated components and confirm correct system behavior across hardware boundaries. Testbench Development and Build Flows - Testbench Infrastructure: Define, implement, and maintain system-level testbenches covering subsystem and full-chip verification scenarios. - Build Flow Management: Own and manage testbench build flows, ensuring reproducibility, scalability, and integration with the broader verification environment. Chip Feature Implementation - Hardware Security: Implement chip-level security features, including secure boot, hardware root of trust, and cryptographic accelerator integration. - Inter-Subsystem Communication: Define and implement communication fabrics and protocols between chip subsystems, including AMBA-based interconnects (AXI, AHB, APB). - Power Management: Implement hardware power management features, including power domain control, clock gating, and low-power state transitions. - Boot Flow and Configuration: Define and implement the chip boot architecture, including reset sequencing, configuration registers, and boot ROM integration.