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Director role driving signal integrity and power integrity for Netpreme's first-generation MPU, covering system-level SI/PI architecture and design guidelines. The work includes end-to-end channel simulation, SI/PI analysis of DDR5, LPDDR5 and LPDDR6 interfaces, and correlation of simulations with lab measurements. Tools named include ADS and HFSS, with HSPICE a plus.
The biggest bottleneck in AI systems today is memory. Chips compute faster than they can be fed data—a problem known as the memory wall—and Netpreme is building the solution that allows AI memory to scale independently of AI compute. Our approach spans the full stack, from a proprietary memory management framework at the XPU kernel and OS levels to X-Mem™, the world’s first Memory Processing Unit (MPU) silicon. Founded by MIT researchers at the intersection of optical networking, ML systems, and GPU kernel optimization, we’re based in Cambridge, MA, and Santa Clara, CA. We’re looking for people who want to own hard problems end to end—and help shape the next generation of AI systems.
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We are seeking a Director to drive Signal Integrity, Power Integrity of our first generation MPU. It involves all aspects for SI/PI from silicon to system.
This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.
