Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads.

Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter!

If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders.

Lightmatter is (re)inventing the future of computing with light!

We're looking for a hands-on Photonics engineer to lead verification and characterization of high-speed electro-optic links across multiple silicon and system programs. You'll work at the bench alongside the EOE team owning modeling methodology, measurement standards, and serving as the escalation point for the toughest signal integrity and link-performance problems in the org.

Responsibilities:

• Run hands-on lab characterization and debug of high-speed electrical/optical hardware, including novel failure modes
• Build system-level electrical/optical/EO channel models and correlate them against your own bench measurements
• Own link budget and verification methodology while staying hands-on with the validating measurements
• Characterize eye diagrams, BER, jitter, equalization, and channel impairments
• Support silicon bring-up and root-cause debug with analog, package, PCB, and SerDes teams
• Influence chip/package/system architecture tradeoffs based on bench findings
• Mentor Senior/Staff engineers without stepping back from lab work
• Build automation/tools to speed up characterization work

Qualifications:

• MS/PhD in EE, Photonics, Physics (8+ yrs) or BS/MS (10+ yrs)
• Ownership of verification strategy for a full silicon/system program
• Deep expertise in 56G/112G/224G+ serial links, SerDes equalization (CTLE/FFE/DFE), and signal integrity (S-parameters, crosstalk, link budgets)
• Hands-on lab experience leading investigations that stalled others
• Strong Python/MATLAB for team-used automation frameworks