Digital - Digital Design Engineer (title will reflect experience)
Eliyan · Bay Area, Vancouver or Toronto
Extracted from the posting
Digital Design Engineer at Eliyan developing micro-architecture and SystemVerilog RTL for Ethernet PCS/PMA IPs at 100G, 200G, 400G, and 800G. The role covers IEEE 802.3 compliance, synthesis to a PPA-optimized netlist, and IP collateral including SDC, UPF/CPF, and LINT/CDC rule files. Work is done with verification and physical design teams.
Join the leading chiplet startup! As an Eliyan digital designer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing micro-architecture specifications and RTL design descriptions for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. MUST BE WILLING TO WORK ONSITE - M-F
Key Responsibilities
- Design, develop and/or integrate Ethernet PCS/PMA IPs for various data rates (100/200/400/800G)
- Develop micro-architecture specifications and implement digital designs using SystemVerilog
- Ensure compliance with Ethernet standards (IEEE 802.3)
- Optimize designs for power, area, and performance
- Collaborate with verification engineers for IP verification
- Work closely with physical design team for physical implementation
- Participate in design reviews and ensure design quality
- Develop and maintain all IP design collaterals that include documentation, RTL, SDC constraints, power intent definition (UPF/CPF), LINT/CDC rule files and waivers
- Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
Qualifications
- Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
- 5+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
- Strong expertise in RTL and Assertion coding with SystemVerilog
- Proficiency in taking RTL through synthesis and produce a PPA optimized frontend netlist
- Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training
- Strong bias for innovations across all aspects of digital design including automation of mundane activities and methods for quality improvement
- Experience integrating 3rd party mixed signal IPs
- Proven track record of being part of a start-up like environment
- Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
