Digital - ASIC Design Automation & Integration Engineer
Eliyan · Bay Area, Vancouver or Toronto
Extracted from the posting
ASIC Design Automation and Integration Engineer at Eliyan owning lint, CDC, and synthesis signoff criteria and the waiver management system. The role also covers RTL IP integration, Jenkins-based CI pipelines, IP release packaging, and LLM-based violation triage tooling for the NuLink PHY program. Stack includes SpyGlass, Questa, Genus, Fusion Compiler, SystemVerilog, Python, and Tcl.
Lint / CDC / Synthesis Quality · IP & Chip Integration · AI-Augmented Design Flows · CI/CD for RTL
On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON
Full-Time - Equity Participation - Comprehensive Benefits
ABOUT THE ROLE
Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.
We are looking for an engineer who can own the intersection of design quality, automation, and design integration. In this role you will define and enforce signoff criteria for lint, CDC, and synthesis across all active programs, build the waiver management and tracking infrastructure, and develop AI-augmented tooling that turns thousands of tool violations into actionable, designer-ready reviews. You will report into the digital design team and work directly alongside RTL designers.
Design quality and automation are the core of this role. IP and chip-level integration ownership is scope you can grow into as you ramp — we're looking for someone who wants it.
- Experience building waiver management systems, violation databases, or design quality dashboards.
- Experience with register map automation and IP packaging standards (PeakRDL, SystemRDL, or IP-XACT).
- Knowledge of UPF and power intent.
- Knowledge of Static Timing Analysis.
- Practical experience with LLM APIs or agent frameworks (e.g., Anthropic Claude, OpenAI) applied in a production or team-facing context.
- Hands-on experience integrating and releasing digital IP — hierarchy assembly, connectivity closure, versioned collateral, and handoff to internal or external consumers.
- Exposure to PHY, SerDes, die-to-die interconnect, or chiplet-based SoC design.
- Open-source contributions to design automation, hardware verification, or developer tooling.
